It is common practice in the design of a data processing system with multiple interfaces, such as Ethernet, UART, CODEC, I2C Bus, etc., interfaces, to provide a data buffer, such as a first in/first out (FIFO) buffer, within each of the interface circuits. In this case data is transferred between system memory and the interface circuit buffers by the use of direct memory access (DMA) techniques, or by a central processor unit (CPU) performing read or write operations to remove data from the buffers or to store data in to the buffers. This latter process is sometimes referred to as “programmed I/O”.
As can be appreciated, the use of programmed I/O consumes CPU bandwidth, and thus reduces the amount of time that the CPU can spend on other tasks. This results in a decrease of the effective MIPS (millions of instructions per second) of the CPU. The use of DMA can also be disruptive, as the additional loading of the system data bus can cause the CPU to incur wait states when it attempts to access a resource, such the system memory.